![]() ![]() Select every M1A and M1B shape and then hit the “q” key to edit it’s properties. M1A-to-M1B spacing rules, rather than M1A-to-M1A spacing rules). Instead, we will use M1, which is an “uncolored” layer that uses the most dense spacing rules ( i.e. First, we won’t be using the M1A and M1B layers anymore, since they’re not supported for LVS and parasitic extraction. Use the Library Manager to copy the layout cell-view from that cell into this one. For the fastest results, start with the completed layout from Layout Tutorial 1. When you generate an HSPICE netlist, this node will now have a more meaningful name, rather than something random like “NET41”. The figure shows that the node between the two NMOS transistors has been given the name “X”. Note that you can add a “Wire Name” to internal nodes by selecting Create->Wire Name or by hitting the “l” (lower case “L”) key. 4.2 Extract with Parasitic Capacitances OnlyĬreate a cell called “nand2”, and make a schematic like the one shown below. ![]() 4.1 Extract with Parasitic Capacitances and Resistances.3.1 Perform an LVS Check without Errors.You’ll also perform a parasitic extraction and generate an HSPICE netlist with accurate wire- and source-/drain, adjacent wires capacitances, as well as wire resistances generated from the layout. In this tutorial you will create the schematic and layout for a NAND gate, and then perform a layout-vs.-schematic (LVS) check to verify the connectivity. ![]()
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